In most data communication environments, a number of terminals interact with a master station or central processing unit (CPU) that controls the reception and transmission of data performed by the terminals. For example, FIG. 1 of the drawings illustrates interaction between a host CPU 32 and Intel 82586 LAN controller 34 (coprocessor) in the IEEE 802.3/Ethernet environment. Communication between the host CPU 32 and the controller 34 is carried out via a 82586 system memory 36. The controller comprising a command unit (CU) and receive unit (RU) (not shown in FIG. 1) is engaged in the two types of activities simultaneously: the CU may be fetching and executing commands out of the memory, and the RU may be storing received frames in the memory. CPU intervention is required after the CU executes a command or the RU stores a frame. The CPU and the controller are connected by INTERRUPT and CHANNEL ATTENTION hardware signals. The INTERRUPT signal is used by the controller to inform the CPU as to changes in control and status information. The CHANNEL ATTENTION signal is used by the CPU to inform the controller as to those changes.
The system memory structure consists of four parts: an initialization root 38, a system control block (SCB) 40, a command list 42 and a receive frame area 36. The initialization root 38 is a predetermined location of the memory space known to both the host CPU 32 and the controller 34, is accessed at initialization and points to the SCB 40. The SCB 40 functions as a bidirectional mail drop between the host CPU 32 and the controller 34 to exchange control and status information. The command list 42 stores a program for the CU. The receive frame area 36 comprises a number of receive buffers and their descriptions. The buffers are filled upon frame reception.
Referring to FIG. 2, an IEEE 802.3 frame/packet 200 comprises a preamble 202 and start frame delimiter (SFD) 204 automatically generated by the LAN controller 34 during transmission and prepended to the frame. The destination address 206, source address 208, length field 210 and data field 212 are supplied by the host CPU 32. The frame check sequence (FCS) 214 is cyclic redundancy check data (CRC) computed by the controller 34 and appended at the end of the frame. The FCS 214 may be followed by the end frame delimiter 216 generated by the controller 34 to indicate the lack of a signal after transmitting the last bit of the FCS 214.
The receive frame area 44 is configured by the host CPU to receive data placed by the controller as frames are received. In order to prepare the receive frame area to receive the next frame, the controller interrupts the CPU upon receiving the entire previous frame. Accordingly, the Intel LAN controller provides an interrupt of the CPU per each received frame.
In another example of interaction between a controller and a master processor, an AM7990 LAN controller that is designed to interface a variety of microprocessors to an IEEE 802.3/Ethernet LAN generates an interrupt to the microprocessor upon the reception of each packet.
The growth in computer applications that require heavy data traffic and the growing availability of high-speed transmission lines creates a need for communication systems able to manage the traffic at much higher rates. However, their throughput is limited by the processing power of master processors that are interrupted upon the reception of each frame or packet. High-speed communication systems may require the master processors to be interrupted at rates 20,000-100,000 interrupts per second. To eliminate processing bottlenecks created by the master processors, it would be desirable to provide a communication system able to receive a contiguous sequence of data frames or packets without interrupting a master processor upon the reception of each frame or packet.